ST Chip TM8L151G4U6 QFN28 Microcontroller

Description: 

• The medium-density STM8L151x4/6 and STM8L152x4/6 devices are members of the STM8L ultra-low-power 8-bit family. The medium-density STM8L15x family operates from 1.8 V to 3.6 V (down to 1.65 V at power down) and is available in the -40 to +85 °C and -40 to +125 °C temperature ranges.

• The medium-density STM8L15x ultra-low-power family features the enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations.

• The family includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive In-Application debugging and ultra-fast Flash programming.

• All medium-density STM8L15x microcontrollers feature embedded data EEPROM and low-power, low-voltage, single-supply program Flash memory.

• They incorporate an extensive range of enhanced I/Os and peripherals.

• The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, and simplified even more by the use of a common set of development tools.

• Six different packages are proposed from 28 to 48 pins. Depending on the device chosen, different sets of peripherals are included.

• All STM8L ultra-low-power products are based on the same architecture with the same memory mapping and a coherent pinout.

Parameters:

Operating conditions:

• Operating power supply range 1.8 V to 3.6 V (down to 1.65 V at power down)

• Temp. range: - 40 °C to 85, 105 or 125 °C

Low power features:

• 5 low power modes: Wait, Low power run (5.1 μA), Low power wait (3 μA), Active-halt with full RTC (1.3 μA), Halt (350 nA)

• Consumption: 195 μA/MHz + 440 μA

• Ultra-low leakage per I/0: 50 nA

• Fast wakeup from Halt: 4.7 μs

Advanced STM8 core:

• Harvard architecture and 3-stage pipeline

• Max freq. 16 MHz, 16 CISC MIPS peak

• Up to 40 external interrupt sources

Reset and supply management:

• Low power, ultra-safe BOR reset with 5 selectable thresholds

• Ultra-low-power POR/PDR

• Programmable voltage detector (PVD)

Clock management:

• 1 to 16 MHz crystal oscillator

• 32 kHz crystal oscillator

• Internal 16 MHz factory-trimmed RC

• Internal 38 kHz low consumption RC

• Clock security system

Low power RTC:

• BCD calendar with alarm interrupt

• Auto-wakeup from Halt w/ periodic interrupt

• LCD: up to 4x28 segments w/ step-up converter

Memories:

• Up to 32 KB of Flash program memory and 1 Kbyte of data EEPROM with ECC, RWW

• Flexible write and read protection modes

• Up to 2 Kbyte of RAM

DMA:

• 4 channels; supported peripherals: ADC, DAC, SPI, I2C, USART, timers

• 1 channel for memory-to-memory

• 12-bit DAC with output buffer

• 12-bit ADC up to 1 Msps/25 channels

• T. sensor and internal reference voltage

• 2 ultra-low-power comparators

• 1 with fixed threshold and 1 rail to rail

• Wakeup capability

Timers:

• Two 16-bit timers with 2 channels (used as IC, OC, PWM), quadrature encoder

• One 16-bit advanced control timer with 3 channels, supporting motor control

• One 8-bit timer with 7-bit prescaler

• 2 watchdogs: 1 Window, 1 Independent

• Beeper timer with 1, 2 or 4 kHz frequencies

Communication interfaces:

• Synchronous serial interface (SPI)

• Fast I2C 400 kHz SMBus and PMBus

• USART (ISO 7816 interface and IrDA)

• Up to 41 I/Os, all mappable on interrupt vectors:

• Up to 16 capacitive sensing channels supporting touchkey, proximity, linear touch and rotary touch sensors

Development support:

• Fast on-chip programming and non intrusive debugging with SWIM

• Bootloader using USART

96-bit unique ID